The present invention relates to high density devices. In particular, embodiments of the present invention provide methods for forming contact structure in which conductors connected to multiple active layers in a three-dimensional high density semiconductor device, such as memory device.
Three dimensional (3D) semiconductor devices are characterized by multiple layers forming a stack of alternating active layers and insulating layers. In a memory device, each of the layers can include a planar array of memory cells. For certain three-dimensionally stacked memory devices, active layers can comprise active strips of materials configured as bit lines or word lines for memory cells stacked in spaced-apart ridge-like structures. The active layers can be made from a doped (p-type or n-type) or undoped semiconductor material. In such 3D memory, memory cells can be disposed at the cross-points of the stacked bit lines or word lines and the crossing word lines or bit lines, forming a 3D memory array.
One way of connecting interlayer conductors to the active layers in the stack can be referred to as a multiple lithographic-etch process, disclosed in commonly owned U.S. Pat. No. 8,383,512, entitled Method for Making Multilayer Connection Structure, the disclosure of which is incorporated by reference. Another way of doing so, which can be referred to as a trim-etch process, is disclosed in commonly owned U.S. patent application Ser. No. 13/735,922, filed 7 Jan. 2013, entitled Method for Forming Interlayer Conductors to a Stack of Conductor Layers, the disclosure of which is incorporated by reference.